This invention relates to the field of fabricating semiconductor devices and, more particularly, to maintaining accuracy in their fabrication using step and repeat systems for projecting lithographic object images on a wafer substrate to create an array.
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
Recent developments in the field of semiconductor wafer fabrication have led to advancements in the size reduction of devices present on die of a semiconductor wafer. Such advancements have lead to increasing density of circuit elements in the die structure. As feature sizes and devices become smaller, there is a need to more precisely align the lithographic masks with the wafer during masking steps, minimizing misalignment between layers.
A typical alignment technique will require the use of alignment targets that are defined on a wafer layer preceding the layer to be deposited. With recent microcircuit devices of semiconductor wafers, a large number of patterns are deposited, for example, to form patterned regions of insulative, conductive and differing conductivity materials. For multiple layers, where successive metallized layers are separated by an insulation layer such as an oxide layer, there is a need to align the topography of each layer over the previous layers.
One way of aligning the plurality of layers to be deposited involves the use of alignment patterns comprising an array of alignment markings that are defined on the wafer on each previous layer. In order to ensure alignment between successive layers, it becomes necessary to replicate the positioning of the alignment markings from one layer to the next. The placement of successive circuit structures, in layers, is dependent on the precise placement of a lithographic mask and the alignment markings on the previous layer.
Another way of aligning the plurality of layers to be deposited involves the use of alignment patterns comprising alignment marks, or markings, that are defined on the wafer on an original base layer, with all subsequent layers being aligned with respect to these alignment marks. For example, fabricating integrated circuit structures on a wafer involves successively forming a series of metallized and insulative layers on the wafer, with the aid of the alignment markings. Typically, an insulative layer separates each pair of metallized layers. The use of alignment markings when depositing the layers ensures alignment between layers, enabling replication of a desired topography from layer to layer.
One such system uses a lithographic process that includes a step-and-repeat aligning system with a reticle to form each individual die on a wafer, successively across the wafer. The wafer is usually secured onto a movable stage and the stage is stepped to a new position each time that the image is projected onto the wafer. The process is repeated until all the desired elements of that particular layer are imprinted on the wafer. In creating various layers, the same step and repeat process is used in order that elements at various levels can be properly aligned for proper interconnection. Consequently, stepper systems are monitored frequently for precise and reproducible stage movement and placement. Alignment corrections need to made regularly on the x and y offsets and on the rotation of the stage, to name a few.
One method to measure alignment correction is to use the xe2x80x9cbox in a boxxe2x80x9d approach. In this approach, determining the alignment between successive layers includes printing a first box on one layer into a larger frame of a second box in a lower level or layer. The amount that the inner box is off center relative to the outer frame represents the misalignment from one layer to another. Although the latent image of a box or frame can be used to determine alignment from the top layer to an underlying layer, the contrast is generally poor and/or irreproducible. Attempts have been made to calibrate alignment by processing the dark field image of a latent image superimposed on an alignment artifact. However, the biggest difficulty with this approach has been that the contrast is generally too poor to make this technique sufficiently accurate.
Therefore, there is a need to develop an alignment correction method that is easy to implement and allows for visual verification of proper alignment.
For many years, there has been a recognized need to be able to measure the alignment of an exposed but undeveloped resist onto a prior layer. With this capability, steppers could virtually calibrate themselves by exposing a small portion of the wafer, measuring the alignment of the latent image and adjusting the pattern placement with this information. Accordingly, a method is described herein that addresses this need by measuring alignment in step and repeat systems. The method includes providing a substrate that has a layer of photoresist disposed on it and then forming a first plurality of underlying grating images in the photoresist. The first plurality of images has a repetitive and symmetrical pattern with equal spacing between images. A second plurality of latent grating images is formed in the photoresist having substantially the same pattern of images as the first plurality of images. The second plurality of images is disposed above and offset from the first plurality of images, the first and second plurality of images serving as an indicator of alignment between the step and repeat system and the substrate when the combined images form a series of equally spaced lines.
According to another aspect of the invention, a method for measuring alignment in a step and repeat system includes providing a substrate with a photoresist thereon and a forming a first plurality of underlying grating lines in the substrate, the lines having a predetermined line pitch. A second plurality of latent grating lines is then formed in the photoresist, having substantially the same pattern of lines as the first plurality of lines, the second plurality of lines being disposed above and offset from the first plurality of lines. The first and second plurality of lines combine to form a regular line-space pitch pattern to indicate that the step and repeat system and the substrate are aligned. In another application, for example, in connection with calibrating an alignment system, the grating lines can be formed in the photoresist rather than the substrate.
In yet another aspect of the invention, a stepper apparatus for projecting images on a semiconductor substrate includes a source of energy for generating an energy beam, a reticle element located in the path of the beam and a lens disposed between the beam and the energy beam. The reticle element has a first region with a pattern for generating a first plurality of underlying images on a semiconductor substrate, the pattern is then transferred into the substrate (e.g., by etching), and a second region with a pattern for generating a second plurality of latent images on the semiconductor substrate. The second plurality of images is disposed above and offset from the first plurality of images after formation. The apparatus also includes a mechanism for inspecting alignment of the first and second plurality of images, alignment being indicated by the formation of a pattern of equally spaced lines when the first and second plurality of images are combined.
In yet another aspect of the invention, a system for measuring alignment in a step and repeat system includes an energy beam generator, a substrate positioner for positioning a photoresist coated substrate under the energy beam and an imaging mechanism adapted to receive the energy beam and form images on the substrate. The imaging system forms a first plurality of underlying grating images in the photoresist, the pattern is then transferred into the substrate (e.g., by etching), the images having a repetitive and symmetrical pattern with equal spacing therebetween, and forms a second plurality of latent images on the semiconductor substrate, the second plurality of images disposed above and offset from the first plurality of images. The system also includes an inspection mechanism for inspecting alignment of the first and second plurality of images, alignment being indicated by the formation of a pattern of equally spaced lines when the images are combined.
The above summary is not intended to provide an overview of all aspects of the present invention. Other aspects of the present invention are exemplified and described in connection with the detailed description.